ISMVL 2017
IEEE International Symposium
on MultipleValued Logic
on MultipleValued Logic
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Tentative Program
Sunday, May 21, 2017  
9:009:15  Registration  
9:1517:40  Workshop on PostBinary ULSI Systems  
Monday, May 22, 2017  
9:009:15  Opening  
9:1510:00  [Keynote Address I]  
An Algorithm for Constraint Satisfaction Problem Dmitriy Zhuk (Moscow State University, Russia) 

10:0010:15  Coffee Break  
10:1511:55  [1A. Signal Processing & VLSI Design]  [1B. Algebra & Logic I] 
AnalogtoDigital Converters Using not MultiLevel but MultiBit Feedback Paths T. Waho 
Phase Semantics for Multilattice Formalism N. Kamide 

A PAM4 Eye Diagram Analysis and Its Monitoring Technique for Adaptive PreEmphasis for MultiValued Data Transmission Y. Yuminaka, T. Kitamura, and Y. Iijima 
Median Based Calculus for Lattice Polynomials and Monotone Boolean Functions M. Couceiro, P. Mercuriali, R. Péchoux, and A. Saffidine 

FineGrain Pipelined Reconfigurable VLSI Architecture Based on MultipleValued Multiplexer Logic K. Shimabukuro and M. Kameyama 
Posets of Minors of Functions in MultipleValued Logic E. Lehtonen and T. Waldhauser 

A Novel Ternary Multiplier Based on Ternary CMOS Compact Model Y. Kang, J. Kim, S. Kim, S. Shin, E. Jang, J. W. Jeong, K. R. Kim, and S. Kang 
Extending Ideal Paraconsistent FourValued Logic N. Kamide 

11:5513:30  Lunch  
13:3014:15  [Dedication Talk to the Memory of Ivan Stojmenvić]  
A LifeWellSpent in the Service of Science Dan Simovici (University of Massachusetts Boston, USA) 

14:1514:30  Coffee Break  
14:3016:10  [2A. Spectral Techniques]  [2B. Clone Theory]  Special Session  
On Fixed Points of the ReedMullerFourier Transform C. Moraga, R. Stanković, M. Stanković, and Suzana Stojković 
On the Nonexistence of Minimal Strong Partial Clones M. Couceiro, L. Haddad, and K. Schölzel 

Some Spectral Invariant Operations for MultipleValued Functions with Homogeneous Disjoint Products in the Polynomial Form M. Stanković, C. Moraga, and R. Stanković 
On the Interval of Boolean Strong Partial Clones Containing Only Projections as Total Operations M. Couceiro, L. Haddad, V. Lagerqvist, and B. Roy 

Properties of the TwoSided RMF Spectrum of Matrices C. Moraga and R. Stanković 
On an Interval of Slupecki Partial Clones L. Haddad and K. Schölzel 

Towards the Gibbs Characterization of a Class of Quaternary Bent Functions R. Stanković, M. Stanković, J. Astola, and C. Moraga 
Three Classes of Closed Sets of Monomials H. Machida and J. Pantović 

16:1016:25  Coffee Break  
16:2517:40  [3A. Fuzzy Logic]  [3B. Design for Security] 
Hintikka Style Game Rules for SemiFuzzy Quantifiers C. Fermüller and M. Hofer 
Physical Unclonable Functions based on Carbon Nanotube FETs M. Moradi, S. Tao, and R. F. Mirzaee 

Term Models of Horn Clauses over Rational Pavelka Predicate Logic V. Costa and P. Dellunde 
TVLTRNG: SubMicrowatt True Random Number Generator Exploiting Metastability in Ternary Valued Latches S. Tao and E. Dubrova 

NonDeterministic Matrices in Action: Expansions, Refinements, and Rexpansions A. Avron and Y. Zohar 
A Systematic Design of TamperResistant GaloisField Arithmetic Circuits Based on Threshold Implementation with (d + 1) Input Shares R. Ueno, N. Homma, and T. Aoki 

Tuesday, May 23, 2017  
9:1510:00  [Keynote Address II]  
Deep Learning for Autonomous Vehicles Branislav Kisačanin (Nvidia Corporation, USA) 

10:0010:15  Coffee Break  
10:1512:20  [4A. Algorithms & Computational Complexity]  [4B. Reversible Computing] 
Discovery of MultipleValued Bent Functions in Galois Field and ReedMullerFourier Domains M. Radmanović and R. Stanković 
Skipping Embedding in the Design of Reversible Circuits A. Zulehner and R. Wille 

Fast Computation of the Discrete Pascal Transform D. Gajić and R. Stanković 
Exact Synthesis of Ternary Reversible Functions using Ternary Toffoli Gates A. Kole, P. M. N. Rani, K. Datta, I. Sengupta, and R. Drechsler 

Exploiting ManyValued Variables in MaxSAT J. Argelich, C.M. Li, and F. Manya 
Extensions to the Reversible Hardware Description Language SyReC Z. AlWardi, R. Wille, and R. Drechsler 

An Exact Optimization Algorithm for Linear Decomposition of Index Generation Functions S. Nagayama, T. Sasao, and J. Butler 
Study of Reversible Ternary Functions with Homogeneous Component Functions P. Kerntopf, K. Podlaski, C. Moraga, and R. Stanković 

Algebraic and Combinatorial Methods for Reducing the Number of Variables of Partially Defined Discrete Functions J. Astola, P. Astola, R. Stanković, and I. Tabus 

12:2013:30  Lunch  
13:30  Excursion & Banquet  
Wednesday, May 24, 2017  
9:1510:00  [Keynote Address III]  
Index Generation Functions: Minimization Methods Tsutomu Sasao (Meiji University, Japan) 

10:0010:15  Coffee Break  
10:1511:55  [5A. Quantum & Stochastic Computing]  [5B. Algebra & Logic II] 
Natural Deduction for Connexive Paraconsistent Quantum Logic N. Kamide 
The GroupoidBased Logic for Lattice Effect Algebras I. Chajda, H. Länger, and J. Paseka 

Study of GPU Acceleration in Genetic Algorithms for Quantum Circuit Synthesis M. Lukac and G. Krylov 
Centralizing Monoids and the Arity of Witnesses H. Machida and I. Rosenberg 

On the Fault Tolerance of Stochastic Decoders A. Hussein, M. Elmasry, and V. Gaudet 
Computing Uniform Interpolants in Nilpotent Minimum Logic D. Valota 

Evaluation of Stochastic Cascaded IIR Filters N. Onizawa, S. Koshita, S. Sakamoto, M. Kawamata, and T. Hanyu 
Nomura Parameters for Sthreshold Functions I. Prokić and J. Pantović 

11:5513:30  Lunch  
13:3014:15  [Dedication Talk to the Memory of Bogdan Falkowski]  
In Memoriam Bogdan Falkowski Claudio Moraga (Technical University of Dortmund, Germany) 

14:1514:30  Coffee Break  
14:3015:45  [6A. Decision Diagrams]  [6B. Logic & Physical Synthesis] 
Error Bounded Exact BDD Minimization in Approximate Computing S. Froehlich, D. Grosse, and R. Drechsler 
Classifying Functions with Exact Synthesis W. Haaswijk, E. Testa, M. Soeken, and G. De Micheli 

MultiValued Decision Diagrams for koutofn ThreeState Systems M. Kvassay, E. Zaitseva, V. Levashenko, and J. Kostolny 
ORInverter Graphs for the Synthesis of Optical Circuits A. Deb, R. Wille, and R. Drechsler 

A Random Forest Using a MultiValued Decision Diagram on an FPGA H. Nakahara, A. Jinguji, S. Sato, and T. Sasao 
CMOSCompatible Ternary Device Platform for Physical Synthesis of MultiValued Logic Circuits S. Shin, E. Jang, J. W. Jeong, and K. R. Kim 

15:4516:00  Coffee Break  
16:0017:40  Plenary Session & Closing  
Thursday, May 25, 2017  
9:009:15  Registration  
9:1517:40  ReedMuller 2017 Workshop 
The Technical Committee on MultipleValued Logic of the IEEE Computer Society will hold its 47th annual symposium in Novi Sad, Serbia, from May 22 to 24, 2017.
The program consists of three invited talks and 45 highquality papers. It offers you a great opportunity to follow the recent technologies and explore future directions in multiplevalued logic and its related areas.
Tentative Program