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ISMVL 2020
IEEE International Symposium
on Multiple-Valued Logic
Hitotsuba Shrine  Takachiho Gorge  Mango

ISMVL 2020, May 20-22 Nov. 9 - 11, 2020, Miyazaki, Japan

Thank You for Attending the 1st Hybrid Symposium!
See You Next Year

The Technical Committee on Multiple-Valued Logic of the IEEE Computer Society will hold its 50th annual symposium in Miyazaki, Japan, on Nov. 9-11, 2020.

Online Presentation (VIDEOs & LIVE):

The on-demand VIDEOs for presentations can be accessed from October 26 to November 27. And, the LIVE sessions will start at 9:00 am on November 9 (JST).

To access the VIDEOs, please click on the link and enter the ID & Password*.
* ID & Password have been sent to registerers via email.

To access the LIVE sessions, please click on the Zoom address that has been sent to registerers via email on Oct. 31, 2020.

Please make sure of the schedule of sessions.
Note that an author of each paper MUST participate in the LIVE session where the paper is scheduled.

In order to access the on-demand video and the live sessions, you must have a paid registration to the Symposium.

Proceedings are available now!

The online proceedings for ISMVL 2020 are available here.

To access the proceedings, user ID and password are necessary.
The ID and password have been sent to registered authors via email. For general attendees, they will be sent in around the beginning of Nov., 2020.

The registration site is here.


The symposium will bring together researchers from computer science, engineering, mathematics, and further disciplines to discuss new developments and directions for future research in the area of multi-valued logic and related fields. Research papers, surveys, or tutorial papers on any subject in these areas are within the scope of the symposium.

The proceedings of ISMVLs are in the Ei compendex that is the broadest and most complete engineering literature database available in the world.

Keynote Speakers:

The following keynote speakers will present their cutting-edge research:

Prof. Masayuki Ohzeki
(Tohoku University, Tokyo Institute of Technology, Japan)

Title: Quantum Annealing and Its Application to Real World

Quantum annealing is a generic solver of combinatorial optimization problem and is implemented by a hardware known as the D-Wave quantum annealer.
    In this talk, we introduce future directions of its application, while showing several practical applications, namely the control of the automated guided vehicles in factory and evacuation system from disaster after big earthquake etc.

Prof. Ali Sheikholeslami
(University of Toronto, Canada)

Digital Annealer: A Stochastic Search for Global Optimum

As Moore's law nears the end of its time, the search for continued improvement in performance has focused on the architecture-level and system-level innovations. At the system level, we resort to stochastic moves to solve hard optimization problems, where the goal is to minimize (or maximize) a function of many variables (in the order of 1000's) in a fraction of a second. These optimization problems are predominant in engineering, health, finance, and environment. In engineering, for example, we often wish to allocate resources to tasks, or schedule tasks given limited resources, to minimize waste. In health, we wish to maximize radiation to a tumor in a patient's body while sparing the healthy organs surrounding the tumor. This indeed requires optimization of the density of an X-ray beam as it rotates 360 degrees around the patient.
    In this keynote speech, we will walk you through a stochastic journey of a Markov Chain Monte Carlo (MCMC) process where we try to find the global minimum of a quadratic function of 1024 binary variables. We will demonstrate how employing several techniques in hardware parallelism including parallel tempering (deploying several parallel hardware blocks exploring the solution space at various "temperatures" and occasionally exchanging their states), parallel trial, and parallel update, can provide significant speedup, allowing CMOS to live far beyond the end of CMOS scaling.

Dr. Alan Mishchenko
(University of California Berkeley, USA)

Title: Boolean Logic Networks for Machine Learning

This talk explores the use of logic networks and Boolean methods in machine learning (ML). Both synthesis and verification are addressed. On the synthesis side, we introduce a novel ML model based on logic networks, which can potentially replace neural networks in some applications. The advantages are, substantially reduced evaluation latency, simpler hardware implementation (no need for memories and arithmetic operations), straight-forward design automation. The challenge is, matching the accuracy of neural networks. On the verification side, we use logic networks, in particular, and-inverter graphs (AIGs), to detect overfitting in any ML model using only the AIG representation of the model and the training data, assuming that the evaluation data is not available or cannot be trusted.

Accompanying Workshop

In conjunction with the symposium, the following workshop will be held.

» 29th International Workshop on Post-Binary ULSI Systems (Nov. 11, 2020)

The 50th International Symposium will take place from Nov. 9 to 11, 2020 in Miyazaki, Japan. Interested researchers are invited to participate the symposium!


IEEE      Computer Society      TC on MVL      Japan MVL


Tateisi Science and
	  Technology Foundation      NICT

SECOM Science and
	  Technology Foundation      The Telecommunications
	  Advancement Foundation


» PDF of Final Program was added on Oct. 31, 2020.

» Access Information for LIVE Presentations was sent vie email on Oct. 31, 2020.

» Site for Video Presentations was added on Oct. 26, 2020.

» Registration Page was updated on Sep. 15, 2020.

» Final Program was added on Sep. 14, 2020.

» Information on Keynote Speakers has been added on Oct. 24, 2019.

» This site was open on May 23, 2019.

» Paper Submission Deadline:
   November 1, 2019 (extended!)
   Abstract: November 23, 2019
   Manucript: November 30, 2019

» Notification of Acceptance:
   February 3, 2020

» Camera-Ready Version:
   March 1, 2020

» Author Registration Deadline*:
   March 8, 2020
   *It is NOT going to be extended!

» Videos for Presentation Deadline:
   October 2, 2020

» Early Registration Deadline:
   April 21, 2020 (postponed!)
   October 10, 2020

» Symposium:
   May 20-22, 2020 (postponed!)
   November 9-11, 2020

» ULSI Workshop:
   May 19, 2020 (postponed!)
   November 11, 2020

» Journal of Applied Logics
  Special Issue (Submission
    August 25, 2020 (extended!)
    September 25, 2020

» IEICE Transactions Special
   Issue (Submission Deadline):
    August 28, 2020 (extended!)
    September 30, 2020

|Final Program|