| 14:30-14:50 | Opening Address |
| Session 1a: | Design and Testing |
| Session Chair: | Prof. Hong-Bok Song (Dongeui University) |
| 14:50-15:15 | On Asynchronous Data-Flow Computer [J-16] |
| Chikatoshi Yamada and Yasunori Nagata | |
| University of the Ryukyus, Japan | |
| 15:15-15:40 | A Circuit Gate Delay Testing Based on Neural Network Diagnosis [J-22] |
| Hisayuki Tatsumi, Yasuyuki Murai, and Shinji Tokumasu | |
| Kanagawa Institute of Technology, Japan | |
| 15:40-16:05 | A Study on Construction of the Parallel Multiplier over Galois Field [K-01] |
| Kwang-Hee Lee, Jong-Hak Hwang, and Heung-Soo Kim | |
| Inha University, Korea | |
| Session 1b: | Signal and Image Processing |
| Session Chair: | Prof. Takao Waho (Sophia University) |
| 14:50-15:15 | Design of Multi-Valued Hybrid FFT Processor Using Parallel PD Circuits [K-09] |
| Myung-Woong Seo*, Gyeong-Yeon Cho**, and Hong-Bok Song* | |
| * Dongeui University, Korea | |
| ** Pukyong National University, Korea | |
| 15:15-15:40 | The Image Contours Extraction with the Ternary 2-Digit Output System Using Laplacian-Gaussian Filter [J-10] |
| Takanori Ashida, Kouichiro Tuji, Masataka Tokumaru, | |
| Noriaki Muranaka, and Shigeru Imanishi | |
| Kansai University, Japan | |
| 15:40-16:05 | Image Segmentation with Clustering Based on Rough Sets [J-05] |
| Takehiko Matsuura*, Syoji Kobashi*, Yutaka Hata*, and Kazuharu Yamato** | |
| *Himeji Institute of Technology, Japan | |
| **Hyogo University, Japan | |
| 16:05-16:20 | Coffee Break (15 min.) |
| Session 2a: | Hardware Algorithms and Circuits |
| Session Chair: | Prof. Takahiro Hanyu (Tohoku University) |
| 16:20-16:45 | A Study on the Design of Highly Parallel Multiplier Using PLA Structure over GF(3m) [K-02] |
| Gi-Young Byun*, Hyeon-Kyeong Seong**, and Heung-Soo Kim* | |
| * Inha University, Korea | |
| ** Sangji University, Korea | |
| 16:45-17:10 | An Implementation of Adder and Multiplier over GF(3) Using the Current-Mode T-Gate [K-03] |
| Byung-Hee Yoon*, Dong-Young Park**, and Heung-Soo Kim* | |
| * Inha University, Korea | |
| ** Wonju National Junior College, Korea | |
| 17:10-17:35 | Counter Tree Diagrams for Fast Addition Algorithms [J-24] |
| Jun Sakiyama, Takafumi Aoki, and Tatsuo Higuchi | |
| Tohoku University, Japan | |
| Session 2b: | Theoretical Aspects of Intelligent Systems |
| Session Chair: | Prof. Yutaka Hata (Himeji Institute of Technorogy) |
| 16:20-16:45 | MVL-Automata for General Purpose Intelligent Model [K-12] |
| Doo-Ywan Kim, Chang-Sik Son, and Hwan-Mook Chung | |
| Catholic University of Daegu, Korea | |
| 16:45-17:10 | Multi-Interval Truth Valued Logic [J-02] |
| Noboru Takagi*, Hiroaki Kikuchi**, and Kyoichi Nakashima* | |
| *Toyama Prefectural University, Japan | |
| **Tokai University, Japan | |
| 17:10-17:35 | Functionally Complete Kleenean Functions [J-04] |
| Yoshinori Yamamoto | |
| Takasaki City University of Economics, Japan |
| Session 3a: | High-Performance Circuits |
| Session Chair: | Dr. Yasushi Yuminaka (Gunma University) |
| 9:00-9:25 | A Study of the Expansion of 4-Digit CMOS Quaternary to Analog Converter [K-08] |
| Sung-Il Han*, Jai-Seok Choi**, and Heung-Soo Kim* | |
| * Inha University, Korea | |
| ** Induk Institute of Technology, Korea | |
| 9:25-9:50 | Performance Estimation of Flash Analog-to-Digital Converter Using Resonant-Tunneling MML/MOBILE Logic Gates [J-07] |
| Kazufumi Hattori, Yuuji Takamatsu, and Takao Waho | |
| Sophia University, Japan | |
| 9:50-10:15 | Current-Mode Differential Circuit for High-Performance Multi-Valued Logic Circuits [J-09] |
| Kiyoko Maruyama, Masashi Nagasato, Koichi Tanno, and Okihiko Ishizuka | |
| Miyazaki University, Japan | |
| Session 3b: | Artificial Intelligence |
| Session Chair: | Prof. Masayuki Matsumoto (Toyo University) |
| 9:00-9:25 | Manufacturing Line Optimization Using Artificial Neural Networks [K-13] |
| Kyung-Ok Choi, Chul-Whei Her, and Hwan-Mook Chung | |
| Catholic University of Daegu, Korea | |
| 9:25-9:50 | Search of Robot Passage Routes Using Fuzzy Distance Measure under Known Environment [J-19] |
| Takaya Matsuda, Tomohiro Kuki, Hisayuki Tatsumi, and Shinji Tokumasu | |
| Kanagawa Institute of Technology, Japan | |
| 9:50-10:15 | Search of Robot Passage Routes Using Fuzzy Sensing Algorithm under Unknown Environment [J-20] |
| Tomohiro Kuki, Yasuyuki Murai, Hisayuki Tatsumi, and Shinji Tokumasu | |
| Kanagawa Institute of Technology, Japan | |
| 10:15-10:45 | Coffee Break (30min.) |
| Session 4a: | Arithmetic Circuits |
| Session Chair: | Prof. Hyeon-Kyeong Seong (Sangji University) |
| 10:45-11:10 | Binary Redundant Addition-Decoder Based on the 2-Bits Block [J-01] |
| Tomohiro Suzuki, Shouta Kawarazaki, and Fumio Wakui | |
| Nihon University, Japan | |
| 11:10-11:35 | On Sharing with Floating Gates of Neuron MOSFET in Quaternary Full Adder with Singed Digit Number Representation [J-06] |
| Atsushi Asaka, Shigeru Imanishi, and Noriaki Muranaka | |
| Kansai University, Japan | |
| 11:35-12:00 | A 8x8-Bit Parallel Multiplier Using Current-Mode CMOS Multiple-Valued Logic Circuits [K-10] |
| Yong-Sup Lee* and Jeong-Beom Kim** | |
| * Hynix Semiconductor Inc., Korea | |
| ** Kangwon National University, Korea | |
| Session 4b: | Fuzzy Logic |
| Session Chair: | Dr. Tomoyuki Araki (Kanagawa Institute of Technology) |
| 10:45-11:10 | A Tuning Method for the Membership Functions of Fuzzy Controller [K-05] |
| Wen-zhe Che and Heung-Soo Kim | |
| Inha University, Korea | |
| 11:10-11:35 | Automatic Drawing of a Fuzzy Graph [J-12] |
| Yoshinori Ueda, and Masayuki Matsumoto | |
| Toyo University, Japan | |
| 11:35-12:00 | Classes of Fuzzy Linguistic Truth Value to be de Morgan Bisemilattice [J-11] |
| Hiroaki Kikuchi* and Noboru Takagi** | |
| *Tokai University, Japan | |
| **Toyama Prefectural University, Japan | |
| 12:00-13:30 | Lunch |
| Session 5a: | Signal Processing and Communication |
| Session Chair: | Prof. Yasunori Nagata (University of the Ryukyus) |
| 13:30-13:55 | A 16x16 Modified Booth Multiplier Using Current-Mode CMOS Multiple-Valued Logic Circuits [K-11] |
| Eun-Sil Lee and Jeong-Beom Kim | |
| Kangwon National University, Korea | |
| 13:55-14:20 | The Positivity Conditions for Multi-Variable Polynomials [J-03] |
| Sadayoshi Takahashi and Kenji Nakajima | |
| Kanagawa Institute of Technology, Japan | |
| 14:20-14:45 | Multiple-Valued Code-Division Multiple Access Techniques for Intra-Chip Communication [J-15] |
| Yasushi Yuminaka and Shinya Sakamoto | |
| Gunma University, Japan | |
| Session 5b: | Logic Design and Algebra |
| Session Chair: | Prof. Jai-Seok Choi (Induk Institute of Technology) |
| 13:30-13:55 | A Circuit Design of the Ternary Logic Gates and Flip-Flop Using the Gates [K-07] |
| Young-Hee Choi*, Jong-Hun Kim**, and Heung-Soo Kim** | |
| * Jaeneung College, Korea | |
| ** Inha University, Korea | |
| 13:55-14:20 | Variable Selection Heuristics for Efficient Decision Trees Construction -- A Survey -- [J-14] |
| Masahiro Miyakawa | |
| Tsukuba College of Technology, Japan | |
| 14:20-14:45 | Clarifying the Independent and Complete Sets of the Axioms of Boolean Algebra in Multiple-Valued Logic [J-18] |
| Tomoko Ninomiya* and Masao Mukaidono** | |
| *Tamagawa University, Japan | |
| **Meiji University, Japan | |
| 14:45-15:00 | Coffee Break (15 min.) |
| Session 6: | Invited Address 1 |
| Session Chair: | Prof. Masao Mukaidono (Meiji University) |
| 15:00-16:00 | Galois Connection between Clones and Monoids -- General Idea and Some Specific Results -- |
| Hajime Machida | |
| Hitotsubashi University, Japan | |
| 16:00-16:15 | Coffee Break (15 min.) |
| Session 7: | Invited Address 2 |
| Session Chair: | Prof. Okihiko Ishizuka (Miyazaki University) |
| 16:15-17:15 | History of Nango Village of Miyazaki -- Cultural Exchange between Korea and Japan -- |
| Sumio Harada | |
| Nango Village Office, Miyazaki, Japan | |
| 17:15-17:45 | Plenary Session |
| 19:00- | Conference Banquet |
| Session 8a: | New Circuit Technology |
| Session Chair: | Prof. Dong-Young Park (Wonju National College) |
| 9:00-9:25 | A Circuit Design of Quaternary to Binary and Binary to Quaternary Converter [K-04] |
| Ho-Kyong Lee*, Seung-Yong Park**, and Heung-Soo Kim* | |
| * Inha University, Korea | |
| ** Jaeneung College, Korea | |
| 9:25-9:50 | Dynamic-Storage-Based Multiple-Valued Logic-in-Memory Circuit and Its Application [J-13] |
| Hiromitsu Kimura, Takahiro Hanyu, and Michitaka Kameyama | |
| Tohoku University, Japan | |
| 9:50-10:15 | Voltage-Mode Multi-Input MIN and MAX Circuits for Multi-Valued Logic Circuits [J-08] |
| Kenya Kondo, Hiroshi Magata, Motoi Inaba, Koichi Tanno, and Okihiko Ishizuka | |
| Miyazaki University, Japan | |
| Session 8b: | Computer Aided Design and Applications |
| Session Chair: | Dr. Noboru Takagi (Toyama Prefectural University) |
| 9:00-9:25 | Game-Theoretic Algorithm to Rectilinear Blocks Layout Problem [J-21] |
| Yasuyuki Murai, Hisayuki Tatsumi, and Shinji Tokumasu | |
| Kanagawa Institute of Technology, Japan | |
| 9:25-9:50 | Formal Definition of the Functional Verification Procedure for Arithmetic Description Language: ARITH [J-23] |
| Masahiro Sekine, Takafumi Aoki, and Tatsuo Higuchi | |
| Tohoku University, Japan | |
| 9:50-10:15 | A Study on the Generation Method of the Generalized Reed-Muller Coefficients Using Triangle Cell [K-06] |
| Gi-Soo Na, Sang-Wan Kim, and Heung-Soo Kim | |
| Inha University, Korea | |
| 10:15-10:40 | Automatic Inference Using MacLaurin's Expansion of Fuzzy Logic Function [K-14] |
| Kyung-Sook Lee, Jin-Hee Park, and Hwan-Mook Chung | |
| Catholic University of Daegu, Korea | |
| 10:40-10:50 | Closing Remark |