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ISMVL 2021
IEEE International Symposium
on Multiple-Valued Logic
   

Final Program (Online via Spatial.Chat)

  • 3 invited talks and 7 regular sessions
  • Each invited talk: 45 min. including Q&A
  • Each regular session has 5 regular talks
  • A regular talk: 5-min short presentation & 5-min Q&A
  • To access the online platform and presentation video, registration is required.

Monday, May 24, 2021
CEST UTC PDT CDT EDT JST Contents
15:00 13:00 6:00 8:00 9:00 22:00 ACeSYRI PhD Forum
 
Tuesday, May 25, 2021
CEST UTC PDT CDT EDT JST Contents
13:00 11:00 4:00 6:00 7:00 20:00 Opening
13:15 11:15 4:15 6:15 7:15 20:15 [Invited Talk I]   Chair: Martin Lukac
Unconventional Computing

Prof. Andrew Adamatzsky (University of the West of England Bristol, United Kingdom)
14:00 12:00 5:00 7:00 8:00 21:00 20-min. Break (Discussion)
14:20 12:20 5:20 7:20 8:20 21:20 [Session 1]   Chair: Takashi Hirayama
Bent & Classification Functions
15:10 13:10 6:10 8:10 9:10 22:10 20-min. Break (Discussion)
15:30 13:30 6:30 8:30 9:30 22:30 [Session 2]   Chair: Mike Behrisch
Non-classical Logic
16:20 14:20 7:20 9:20 10:20 23:20 20-min. Break (Discussion)
16:40 14:40 7:40 9:40 10:40 23:40 [Session 3]   Chair: Jan Paseka
Algebra & Formal Aspects
17:30 15:30 8:30 10:30 11:30 0:30 Symposium & TCMVL Meeting (30 min.)
 
Wednesday, May 26, 2021
CEST UTC PDT CDT EDT JST Contents
6:00 4:00 21:00
(May 25)		 23:00
(May 25)		 0:00 13:00 [Invited Talk II]   Chair: Martin Lukac
Quantum Information Processing Using Integrated Photonics

Prof. Nobuyuki Matsuda
(Tohoku University, Japan)
6:45 4:45 21:45 23:45 0:45 13:45 20-min. Break (Discussion)
7:05 5:05 22:05 0:05 1:05 14:05 [Session 4]   Chair: Kaitlin Smith
Quantum & Reversible Circuits
7:55 5:55 22:55 0:55 1:55 14:55 20-min. Break (Discussion)
8:15 6:15 23:15 1:15 2:15 15:15 [Session 5]   Chair: Martin Lukac
Machine Learning Hardware
 
Thursday, May 27, 2021
CEST UTC PDT CDT EDT JST Contents
13:00 11:00 4:00 6:00 7:00 20:00 [Invited Talk III]
  Chair: Jovanka Pantović
Minimal Taylor Clones

Prof. Libor Barto
(Charles University, Czech Republic)
13:45 11:45 4:45 6:45 7:45 20:45 20-min. Break (Discussion)
14:05 12:05 5:05 7:05 8:05 21:05 [Session 6]   Chair: Shinobu Nagayama
Security & Hardware Design
14:55 12:55 5:55 7:55 8:55 21:55 20-min. Break (Discussion)
15:15 13:15 6:15 8:15 9:15 22:15 [Session 7]   Chair: Naoya Onizawa
Circuits & Systems
16:05 14:05 7:05 9:05 10:05 23:05 20-min. Break (Discussion)
16:25 14:25 7:25 9:25 10:25 23:25 Plenary & Closing (30 min.)
 
Friday, May 28, 2021
CEST UTC PDT CDT EDT JST Contents
6:00 4:00 21:00
(May 27)		 23:00
(May 27)		 0:00 13:00 Workshop on Post-Binary ULSI Systems
13:00 11:00 4:00 6:00 7:00 20:00 Reed-Muller Workshop



Papers in Sessions

[Session 1]   Chair: Takashi Hirayama
Bent & Classification Functions
Construction of Ternary Plateaued Functions from Quadratic Forms for Ternary Bent Functions
Milena Stanković, Claudio Moraga and Radomir Stanković
Remarks on Peculiar Properties of Ternary Bent Functions and Construction Algorithms
Radomir Stanković, Milena Stanković, Claudio Moraga and Jaakko Astola
Improvement in the Quality of Solutions of a Heuristic Linear Decomposer for Index Generation Functions
Shinobu Nagayama, Tsutomu Sasao and Jon Butler
Linear Decompositions for Multi-Valued Input Classification Functions
Tsutomu Sasao and Jon Butler
 
[Session 2]   Chair: Mike Behrisch
Non Classical Logic
Symmetric Paraconsistent Quantum Logic
Norihiro Kamide
Linear Orthogonality Spaces as a New Approach to Quantum Logic
Jan Paseka, David Kruml, Thomas Vetterlein and Kadir Emir
Quantales in Circuit Design
Patrik Eklund
Notes on Avron's Self-extensional Four-valued Paradefinite Logic
Norihiro Kamide
A Two-valued Semantics for Infectious Logics
Yang Song, Hitoshi Omori and Satoshi Tojo
 
[Session 3]   Chair: Jan Paseka
Algebra & Formal Aspects
Centralising Monoids with Conservative Majority Operations as Witnesses
Mike Behrisch
Hereditary Rigidity, Separation and Density
Lucien Haddad, Masahiro Miyakawa, Maurice Pouzet and Hisayuki Tatsumi
Proof Systems for Gödel Logics with an Involution
Arnon Avron
Untruth, Falsity and Non-deterministic Semantics
Hitoshi Omori and Daniel Skurt
Multi-valued Decision Diagrams in Reliability Analysis of Consecutive k-out-of-(2k-1) Systems
Miroslav Kvassay, Elena Zaitseva, Peter Sedlacek and Patrik Rusnak
 
[Session 4]   Chair: Kaitlin Smith
Quantum & Reversible Circuits
Lessons Learnt in the Implementation of Quantum Circuit Simulation Using Decision Diagrams
Thomas Grurl, Jürgen Fuß and Robert Wille
Binary, Multi-valued and Quantum Board and Computer Games to Teach Synthesis of Classical and Quantum Logic Circuits
Marek Perkowski and Kyle Liu
Ternary Toffoli-type Reversible Gates: Control Alternatives and Quantum Models
Claudio Moraga
Descending Order Transformation-based Synthesis of MVL Reversible Circuits
Michael Miller and Gerhard Dueck
On Distinguishing Sequences of Several Classes of Reversible Finite State Machines
Martin Lukac and Khaled El-Fakih
 
[Session 5]   Chair: Martin Lukac
Machine Learning Hardware
Quantum Algorithm for Machine Learning and Circuit Design Based on Optimization of Ternary Input, Binary-Output Kronecker-Reed-Muller Forms
Maggie Bao, Cole Powers and Marek Perkowski
A New Approach to Machine Learning Hardware Classifier Design Based on Functional Decomposition of Multi-valued Functions
Saad Al-Askaar and Marek Perkowski
Hierarchical Subspace Learning for Dimensionality Reduction to Improve Classification Accuracy in Large Data Sets
Parisa Abdolrahim Poorheravi and Vincent Gaudet
A High-Throughput Detection Circuit based on 2^q+1-Valued Deep Neural Networks
Naoto Soga, Ryosuke Kuramochi and Hiroki Nakahara
A Design Method for Multiclass Classifiers
Tsutomu Sasao, Yuto Horikawa and Yukihiro Iguchi
 
[Session 6]   Chair: Shinobu Nagayama
Security & Hardware Design
A Formal Approach to Identifying Hardware Trojans in Cryptographic Hardware
Akira Ito, Rei Ueno and Naofumi Homma
An FPGA Implementation of 4x4 Arbiter PUF
Can Aknesil and Elena Dubrova
A Pragmatic Quaternary FPGA Implemented with Floating Gate Memories
Ayokunle Fadamiro, Pouyan Rezaie, Spencer Millican and Christopher Harris
MTMR-SNQM: Multi-Tunnel Magnetoresistance Spintronic Non-volatile Quaternary Memory
Abdolah Amirany, Mohammad Hossein Moaiyeri and Kian Jafari
Synthesis of Asymptotically Optimal Adders for Multiple-Valued Logic
Philipp Niemann and Rolf Drechsler
 
[Session 7]   Chair: Naoya Onizawa
Circuits & Systems
A Practical Implementation of the Ternary Logic Using Memristors and MOSFETs
Jeonggyu Yang, Hyundong Lee, Jae Hoon Jeong, Tae Hak Kim, Sin-Hyung Lee and Taigon Song
An Optimal Design Methodology of Ternary Logic in Iso-device Ternary CMOS
Jonghyun Ko, Kwanwoo Park, Suhyeong Yong, Taegam Jeong, Taehak Kim and Taigon Song
Efficient PAM-4 Data Transmisson with Closed Eye Using Symbol Distribution Estimation
Yosuke Iijima and Yasushi Yuminaka
A Multi-level Cascaded Delta-sigma Modulator with Reduced Quantization Noise Leakage
Takao Waho, Tomoaki Koizumi and Hitoshi Hayashi
Quantum Motions and Emotions for a Humanoid Robot Actor
Richard Deng, Yuchen Huang and Marek Perkowski





The Technical Committee on Multiple-Valued Logic of the IEEE Computer Society will hold its 51st annual symposium in Fully Online, on May 25-27, 2021.

The program consists of three invited talks and 34 high-quality papers in the following sessions:

1. Bent & Classification Functions
2. Non Classical Logic
3. Algebra & Formal Aspects
4. Quantum & Reversible Circuits
5. Machine Learning Hardware
6. Security & Hardware Design
7. Circuits & Systems

It offers you a great opportunity to follow the recent technologies and explore future directions in multiple-valued logic and its related areas.