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IEEE Computer Society, Technical Community on Multiple-Valued Logic


Winners of Outstanding Contributed Paper Award

documents The award winners are as follows:

Year Winner (Paper) Authors
ISMVL 2022 Weak bases for Boolean relational clones revisited M. Behrisch
ISMVL 2021 Construction of Ternary Plateaued Functions from Quadratic Forms for Ternary Bent Functions M. Stanković,
C. Moraga,
R. Stanković
ISMVL 2020 A delta-sigma-modulator feedforward network for a non-binary analog-to-digital converter T. Waho
ISMVL 2019 On a Minimization of Variables to Represent Sparse Multi-Valued Input Decision Functions T. Sasao
ISMVL 2018 An Exact Optimization Method Using ZDDs for Linear Decomposition of Index Generation Functions S. Nagayama,
T. Sasao,
J. T. Butler
ISMVL 2017 Posets of Minors of Functions in Multiple-Valued Logic E. Lehtonen,
T. Waldhauser
ISMVL 2016 An Algebraic Approach to Reducing the Number of Variables of Incompletely Defined Discrete Functions J. Astola,
P. Astola,
R. Stankovic,
I. Tabus
ISMVL 2015 Lazy Clones and Essentially Minimal Groupoids H. Machida,
T. Waldhauser
ISMVL 2014 Outstanding Contributed Paper Award: Relation Graphs and Partial Clones on a 2-Element Set M. Couceiro,
L. Haddad,
K. Schölzel,
T. Waldhauser
Distinctive Contributed Paper Award: Concrete Dualities and Essential Arities S. Kerkhoff
ISMVL 2013 Boolean Max-Co-Clones A. A. Bulatov
ISMVL 2012 Analysis of Multi-State Systems with Multi-State Components Using EVMDDs S. Nagayama,
T. Sasao,
J. T. Butler
ISMVL 2011 The Lattice of the Clones of Self-Dual Functions in Three-Valued Logic D. Zhuk
ISMVL 2010 Completions in Subvarieties of BL-Algebras M. Busaniche,
L. M. Cabrer
Finding Attractors in Synchronous Multiple-Valued Networks Using SAT-based Bounded Model Checking E. Dubrova,
M. Teslenko,
L. Ming
ISMVL 2009 Multiple-Valued Data Transmission Based on Time-Domain Pre-Emphasis Techniques in Consideration of Higher-Order Channel Effects Y. Yuminaka,
Y. Takahashi,
K. Henmi
Generalized Discrete Hartley Transforms C. Moraga
ISMVL 2008 On Maximal Hyperclones on {0, 1} A New Approach H. Machida,
J. Pantović
ISMVL 2007
ISMVL 2006
ISMVL 2005 A Two-Bit-per-Cell Content-Addressable Memory using Single-Electron Transistors K. Degawa,
T. Aoki,
T. Higuchi,
H. Inokawa,
Y. Takahashi
ISMVL 2004 Minimal Partial Hyperclones on a Two-Element Set J. Pantović,
G. Vojvodic
On the Minimization of Average Path Lengths for Heterogeneous MDDs S. Nagayama,
T. Sasao
ISMVL 2003 Cascade Realizations of Two-Valued Input Multiple-Valued Output Functions Using Decomposition of Group Functions T. Sasao
ISMVL 2002
ISMVL 2001
ISMVL 2000 An Efficient Data Transmission Technique for VLSI Systems Based on Multiple-Valued Code-Division Multiple Access Y. Yuminaka,
O. Katoh,
Y. Sasaki,
T. Aoki,
T. Higuchi
ISMVL 1999
ISMVL 1998
ISMVL 1997
ISMVL 1996 A Literal Gate Using Resonant-tunneling Devices T. Waho,
K.J. Chen,
M. Yamamoto
ISMVL 1995 Planar Multiple-Valued Decision Diagrams T. Sasao,
J. T. Butler
ISMVL 1994
ISMVL 1993
ISMVL 1992
ISMVL 1991
ISMVL 1990
ISMVL 1989
ISMVL 1988
ISMVL 1987
ISMVL 1986 On the Optimal Design of Multiple-Valued PLAs T. Sasao