University of
Novi Sad

ISMVL 2017
IEEE International Symposium
on Multiple-Valued Logic

Final Program

Sunday, May 21, 2017
11:00-13:30 Workshop Registration
13:30-17:40 Workshop on Post-Binary ULSI Systems
18:00- ISMVL Registration & Welcome Reception (Restaurant Project 72)
Monday, May 22, 2017
8:00-9:00 ISMVL Registration
9:00-9:15 Opening
9:15-10:00 [Keynote Address I] Chair: H. Machida
An Algorithm for Constraint Satisfaction Problem
Dmitriy Zhuk (Moscow State University, Russia)
10:00-10:15 Coffee Break
10:15-11:55 [1A. Signal Processing & VLSI Design] Chair: N. Onizawa [1B. Algebra & Logic I]
Chair: J. Paseka
Analog-to-Digital Converters Using not Multi-Level but Multi-Bit Feedback Paths
T. Waho
Phase Semantics for Multilattice Formalism
N. Kamide
A PAM-4 Eye Diagram Analysis and Its Monitoring Technique for Adaptive Pre-Emphasis for Multi-Valued Data Transmission
Y. Yuminaka, T. Kitamura, and Y. Iijima
Median Based Calculus for Lattice Polynomials and Monotone Boolean Functions
M. Couceiro, P. Mercuriali, R. Péchoux, and A. Saffidine
Fine-Grain Pipelined Reconfigurable VLSI Architecture Based on Multiple-Valued Multiplexer Logic
K. Shimabukuro and M. Kameyama
Posets of Minors of Functions in Multiple-Valued Logic
E. Lehtonen and T. Waldhauser
A Novel Ternary Multiplier Based on Ternary CMOS Compact Model
Y. Kang, J. Kim, S. Kim, S. Shin, E. Jang, J. W. Jeong, K. R. Kim, and S. Kang
Extending Ideal Paraconsistent Four-Valued Logic
N. Kamide
11:55-13:30 Lunch (Symposium Committee Meeting)
13:30-14:15 [Dedication Talk to the Memory of Ivan Stojmenović]
Chair: L. Haddad
A LifeWell-Spent in the Service of Science
Dan Simovici (University of Massachusetts Boston, USA)
14:15-14:30 Coffee Break
14:30-16:10 [2A. Clone Theory]
- Special Session -

Chair: T. Waldhauser
[2B. Spectral Techniques]
Chair: M. Miller
On the Nonexistence of Minimal Strong Partial Clones
M. Couceiro, L. Haddad, and K. Schölzel
On Fixed Points of the Reed-Muller-Fourier Transform
C. Moraga, R. Stanković, M. Stanković, and Suzana Stojković
On the Interval of Boolean Strong Partial Clones Containing Only Projections as Total Operations
M. Couceiro, L. Haddad, V. Lagerqvist, and B. Roy
Some Spectral Invariant Operations for Multiple-Valued Functions with Homogeneous Disjoint Products in the Polynomial Form
M. Stanković, C. Moraga, and R. Stanković
On an Interval of Slupecki Partial Clones
L. Haddad and K. Schölzel
Properties of the Two-Sided RMF Spectrum of Matrices
C. Moraga and R. Stanković
Three Classes of Closed Sets of Monomials
H. Machida and J. Pantović
Towards the Gibbs Characterization of a Class of Quaternary Bent Functions
R. Stanković, M. Stanković, J. Astola, and C. Moraga
16:10-16:25 Coffee Break
16:25-17:40 [3A. Decision Diagrams]
Chair: R. Stanković
[3B. Fuzzy Logic]
Chair: F. Manyà
Error Bounded Exact BDD Minimization in Approximate Computing
S. Froehlich, D. Grosse, and R. Drechsler
Hintikka Style Game Rules for Semi-Fuzzy Quantifiers
C. Fermüller and M. Hofer
Multi-Valued Decision Diagrams for k-out-of-n Three-State Systems
M. Kvassay, E. Zaitseva, V. Levashenko, and J. Kostolny
Term Models of Horn Clauses over Rational Pavelka Predicate Logic
V. Costa and P. Dellunde
A Random Forest Using a Multi-Valued Decision Diagram on an FPGA
H. Nakahara, A. Jinguji, S. Sato, and T. Sasao
Non-Deterministic Matrices in Action: Expansions, Refinements, and Rexpansions
A. Avron and Y. Zohar
18:30-20:30 Excursion to Petrovaradin Fortress
(meeting point: Clock Tower on the Fortress)
Tuesday, May 23, 2017
9:15-10:00 [Keynote Address II] Chair: J. Pantović
Deep Learning for Autonomous Vehicles
Branislav Kisačanin (Nvidia Corporation, USA)
10:00-10:15 Coffee Break
10:15-12:20 [4A. Algorithms & Computational Complexity]
Chair: M. Stanković
[4B. Reversible Computing]
Chair: G. Dueck
Discovery of Multiple-Valued Bent Functions in Galois Field and Reed-Muller-Fourier Domains
M. Radmanović and R. Stanković
Skipping Embedding in the Design of Reversible Circuits
A. Zulehner and R. Wille
Fast Computation of the Discrete Pascal Transform
D. Gajić and R. Stanković
Exact Synthesis of Ternary Reversible Functions using Ternary Toffoli Gates
A. Kole, P. M. N. Rani, K. Datta, I. Sengupta, and R. Drechsler
Exploiting Many-Valued Variables in MaxSAT
J. Argelich, C.-M. Li, and F. Manya
Extensions to the Reversible Hardware Description Language SyReC
Z. Al-Wardi, R. Wille, and R. Drechsler
An Exact Optimization Algorithm for Linear Decomposition of Index Generation Functions
S. Nagayama, T. Sasao, and J. Butler
Study of Reversible Ternary Functions with Homogeneous Component Functions
P. Kerntopf, K. Podlaski, C. Moraga, and R. Stanković
Algebraic and Combinatorial Methods for Reducing the Number of Variables of Partially Defined Discrete Functions
J. Astola, P. Astola, R. Stanković, and I. Tabus
12:20-13:30 Lunch
13:30-18:30 Excursion to Krusedol Monastery, Sremski Karlovci, and Kis winery
19:30- Banquet (Restaurant Cubo)
Wednesday, May 24, 2017
9:15-10:00 [Keynote Address III] Chair: E. Dubrova
Index Generation Functions: Minimization Methods
Tsutomu Sasao (Meiji University, Japan)
10:00-10:15 Coffee Break
10:15-11:55 [5A. Quantum & Stochastic Computing] Chair: R. Wille [5B. Algebra & Logic II]
Chair: M. Couceiro
Natural Deduction for Connexive Paraconsistent Quantum Logic
N. Kamide
The Groupoid-Based Logic for Lattice Effect Algebras
I. Chajda, H. Länger, and J. Paseka
Study of GPU Acceleration in Genetic Algorithms for Quantum Circuit Synthesis
M. Lukac and G. Krylov
Centralizing Monoids and the Arity of Witnesses
H. Machida and I. Rosenberg
On the Fault Tolerance of Stochastic Decoders
A. Hussein, M. Elmasry, and V. Gaudet
Computing Uniform Interpolants in Nilpotent Minimum Logic
D. Valota
Evaluation of Stochastic Cascaded IIR Filters
N. Onizawa, S. Koshita, S. Sakamoto, M. Kawamata, and T. Hanyu
Nomura Parameters for S-threshold Functions
I. Prokić and J. Pantović
11:55-13:30 Lunch (Technical Committee Meeting)
13:30-14:15 [Dedication Talk to the Memory of Bogdan Falkowski]
Chair: T. Sasao
In Memoriam Bogdan Falkowski
Claudio Moraga (Technical University of Dortmund, Germany)
14:15-14:30 Coffee Break
14:30-15:45 [6A. Design for Security]
Chair: C. Moraga
[6B. Logic & Physical Synthesis] Chair: V. Gaudet
Physical Unclonable Functions based on Carbon Nanotube FETs
M. Moradi, S. Tao, and R. F. Mirzaee
Classifying Functions with Exact Synthesis
W. Haaswijk, E. Testa, M. Soeken, and G. De Micheli
TVL-TRNG: Sub-Microwatt True Random Number Generator Exploiting Metastability in Ternary Valued Latches
S. Tao and E. Dubrova
OR-Inverter Graphs for the Synthesis of Optical Circuits
A. Deb, R. Wille, and R. Drechsler
A Systematic Design of Tamper-Resistant Galois-Field Arithmetic Circuits Based on Threshold Implementation with (d + 1) Input Shares
R. Ueno, N. Homma, and T. Aoki
CMOS-Compatible Ternary Device Platform for Physical Synthesis of Multi-Valued Logic Circuits
S. Shin, E. Jang, J. W. Jeong, and K. R. Kim
15:45-16:00 Coffee Break
16:00-17:40 Plenary Session & Closing
Thursday, May 25, 2017
9:00-9:15 Workshop Registration
9:15-17:40 Reed-Muller 2017 Workshop

Brief Map of the Building

Room A (Amphitheatre):
    Opening, Keynote Addresses, Dedication Talks, Sessions 1A to 6A,
    and Plenary Session & Closing

Room B (Multifunctional Room):
    Sessions 1B to 6B

The Technical Committee on Multiple-Valued Logic of the IEEE Computer Society will hold its 47th annual symposium in Novi Sad, Serbia, from May 22 to 24, 2017.

The program consists of three invited talks and 45 high-quality papers. It offers you a great opportunity to follow the recent technologies and explore future directions in multiple-valued logic and its related areas.

Final Program