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ISMVL 2023
IEEE International Symposium
on Multiple-Valued Logic
     

Call for Participation

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The Technical Committee on Multiple-Valued Logic of the IEEE Computer Society will hold its 53rd annual symposium (ISMVL 2023) in Matsue, Japan, from May 22 to 24, 2023. ISMVL 2023 offers you a great opportunity to follow the recent technologies and explore future directions in multiple-valued logic and its related areas.

Keynote Speakers:

The following keynote speakers will present their cutting-edge research:


Prof. Masato Motomura
(Tokyo Institute of Technology, Japan)

Title: Tackling the Explosions of Data and Solutions with Low-Bitwidth Computing Architectures

Abstract:
AI workloads, in a nutshell, are related to explosions of either data (input to computers) or solutions (output from them). Given the worldwide SGDs consciousness and rapidly expanding AI tasks, those explosions must be handled with as low energy as possible. Hence reducing the bit-width used in such AI tasks as much as possible is getting more critical as it is the best strategy to reduce both the memory and computation energy usage at once. The talk will cover two low-bitwidth design examples: one in a neural network accelerator domain (related to the data explosion) and another in an annealing accelerator domain (associated with the combinatorial explosion of solutions). Algorithm-level, architecture-level, and real-chip-level topics are examined in those design efforts, underling the importance of a holistic approach toward realizing energy-efficient AI computing.


Prof. Takefumi Miyoshi
(QuEL, Inc./e-trees. Japan, Inc./QIQB, Osaka University, Japan)

Title:
A Challenge of Scalable Quantum Computing Control Systems

Abstract:
The speaker is developing a quantum computer controller responsible for managing a large number of quantum bits (qubits) by initializing and manipulating them to facilitate meaningful computations. The controller transmits and receives microwaves to and from the qubits to control and measure their state. Since qubits are incredibly delicate and can be easily disrupted by environmental factors, the controller needs to include highly accurate and stable microwave transceivers.
    The speaker will share some of the key features of our system, including highly accurate microwave transceivers and high-precision synchronous mechanism. To achieve a huge volume quantum computer, a significant number of signal processing systems with analog-to-digital converters (ADCs) and digital-to-analog converters (DACs) to control and measure the qubits are required. However, since the number of channels of ADCs and DACs on a chip is limited, it is necessary to orchestrate multiple signal processing units. The speaker will discuss our architecture for multiple qubit control systems, which is scalable and combines chip-level synchronization by LEMC of JESD204C and system-level synchronization by an IEEE1588-like protocol implemented on an FPGA. This architecture achieves nano-second order synchronization of transmitting and receiving of signal processing units.
    Furthermore, we are continuously striving to improve the performance and efficiency of our system to realize a fault-tolerant quantum computer (FTQC). However, achieving FTQC is a significant challenge, as the controller must be scalable to manage a large number of qubits. The speaker will discuss our ideas and progress on our efforts toward realizing an FTQC.


Prof. Takaaki Mizuki
(Tohoku University, Japan)

Title: Card-based Cryptography: How to Securely Compute Multiple-valued Functions Using a Deck of Cards

Abstract:
Card-based cryptography enables us to perform cryptographic tasks such as secure multiparty computations using a deck of physical cards. For example, the first card-based protocol, called the five-card trick, proposed by Den Boer in 1989 uses a deck of five cards to enable two players, Alice and Bob, each privately holding a one-bit value to know only the AND value of their private bits without revealing them more than necessary. Here, a one-bit value is encoded with a pair of black and red cards: the order of black to red represents 0, and the order of red to black represents 1. A pair of face-down cards of different colors is called a commitment to the corresponding bit under such an encoding rule. Therefore, after players, say Alice and Bob, create commitments to their individual secret bits, a card-based protocol should output the value of some predetermined function via a series of actions such as turning over and shuffling cards. Since the invention of the five-card trick, much effort has been devoted to devising efficient AND, XOR, and copy protocols. Currently, we have several card-based protocols efficient enough for lay-people to easily execute in everyday life. Theoretically, combining these elementary protocols, we can securely compute any functions (including multiple-valued functions). In this talk, I briefly introduce the history of card-based cryptography as well as several useful card-based protocols, which can be easily executed by you.



Technical (Regular) Papers:

Other than the keynote addresses, 37 high-quality technical papers including special sessions will be presented as well. The tentative program is available here.

Accompanying Workshops:

In conjunction with ISMVL 2023, the following workshops will be held.


All participants are required to register. The deadline for early registration is April 20, 2023. Details about registration such as registration fee and how to register are available here.


Travel Support for Students:

We plan to secure some money (around 50,000 Yen) to support students to attend ISMVL 2023. If the first author of the paper is a student and the student is going to present the paper at ISMVL, then he/she is eligible to receive a travel grant. When you are submitting a paper, please indicate whether the first author is a student.



Symposium Chair: Program Chair:
Yasushi Yuminaka
Gunma University, Japan
Email: yuminaka{at}gunma-u.ac.jp
Naofumi Homma
Tohoku University, Japan
Email: naofumi.homma.c8{at}tohoku.ac.jp



» Early Registration Deadline:
   April 20, 2023

» ULSI Workshop:
   May 21, 2023

» ISMVL 2023:
   May 22-24, 2023

» Reed-Muller Workshop:
   May 24, 2023

»Download the Document (PDF)