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ISMVL 2023
IEEE International Symposium
on Multiple-Valued Logic

ISMVL 2023, May 22-24, 2023, Matsue, Shimane, Japan

Thank You Very Much for Attending!
See You Next Year in Brno, Czech Republic

Photos at ISMVL 2023: They are kindly provided by Prof. Tanaka and Prof. Yuminaka.
The photos will be provided until June 30, 2023.

The Technical Community on Multiple-Valued Logic of the IEEE Computer Society will hold its 53rd annual symposium in Matsue, Shimane, Japan on May 22-24, 2023.

Style of holding ISMVL 2023:

We are excited to announce that ISMVL 2023 will primarily be held in-person in Matsue, Japan, allowing for valuable face-to-face discussion and an enjoyable local atmosphere. However, we also understand that the challenges posed by COVID-19 are still ongoing, and therefore, we will provide an online option for attending the conference.

If you are unable to travel to Matsue, please respond to the inquiry form in the email that was sent to all registered participants on around April 27, 2023.

The symposium will bring together researchers from computer science, engineering, mathematics, and further disciplines to discuss new developments and directions for future research in the area of multi-valued logic and related fields. Research papers, surveys, or tutorial papers on any subject in these areas are within the scope of the symposium.
Travel Grant for Students: (Application was closed on April 21, 2023)

The proceedings of ISMVLs are in the Ei compendex that is the broadest and most complete engineering literature database available in the world.

Keynote Speakers:

The following keynote speakers will present their cutting-edge research:

Prof. Masato Motomura
(Tokyo Institute of Technology, Japan)

Title: Tackling the Explosions of Data and Solutions with Low-Bitwidth Computing Architectures

AI workloads, in a nutshell, are related to explosions of either data (input to computers) or solutions (output from them). Given the worldwide SGDs consciousness and rapidly expanding AI tasks, those explosions must be handled with as low energy as possible. Hence reducing the bit-width used in such AI tasks as much as possible is getting more critical as it is the best strategy to reduce both the memory and computation energy usage at once. The talk will cover two low-bitwidth design examples: one in a neural network accelerator domain (related to the data explosion) and another in an annealing accelerator domain (associated with the combinatorial explosion of solutions). Algorithm-level, architecture-level, and real-chip-level topics are examined in those design efforts, underling the importance of a holistic approach toward realizing energy-efficient AI computing.

Prof. Takefumi Miyoshi
(QuEL, Inc./e-trees. Japan, Inc./QIQB, Osaka University, Japan)

Title: A Challenge of Scalable Quantum Computing Control Systems

The speaker is developing a quantum computer controller responsible for managing a large number of quantum bits (qubits) by initializing and manipulating them to facilitate meaningful computations. The controller transmits and receives microwaves to and from the qubits to control and measure their state. Since qubits are incredibly delicate and can be easily disrupted by environmental factors, the controller needs to include highly accurate and stable microwave transceivers.
    The speaker will share some of the key features of our system, including highly accurate microwave transceivers and high-precision synchronous mechanism. To achieve a huge volume quantum computer, a significant number of signal processing systems with analog-to-digital converters (ADCs) and digital-to-analog converters (DACs) to control and measure the qubits are required. However, since the number of channels of ADCs and DACs on a chip is limited, it is necessary to orchestrate multiple signal processing units. The speaker will discuss our architecture for multiple qubit control systems, which is scalable and combines chip-level synchronization by LEMC of JESD204C and system-level synchronization by an IEEE1588-like protocol implemented on an FPGA. This architecture achieves nano-second order synchronization of transmitting and receiving of signal processing units.
    Furthermore, we are continuously striving to improve the performance and efficiency of our system to realize a fault-tolerant quantum computer (FTQC). However, achieving FTQC is a significant challenge, as the controller must be scalable to manage a large number of qubits. The speaker will discuss our ideas and progress on our efforts toward realizing an FTQC.

Prof. Takaaki Mizuki
(Tohoku University, Japan)

Title: Card-based Cryptography: How to Securely Compute Multiple-valued Functions Using a Deck of Cards

Card-based cryptography enables us to perform cryptographic tasks such as secure multiparty computations using a deck of physical cards. For example, the first card-based protocol, called the five-card trick, proposed by Den Boer in 1989 uses a deck of five cards to enable two players, Alice and Bob, each privately holding a one-bit value to know only the AND value of their private bits without revealing them more than necessary. Here, a one-bit value is encoded with a pair of black and red cards: the order of black to red represents 0, and the order of red to black represents 1. A pair of face-down cards of different colors is called a commitment to the corresponding bit under such an encoding rule. Therefore, after players, say Alice and Bob, create commitments to their individual secret bits, a card-based protocol should output the value of some predetermined function via a series of actions such as turning over and shuffling cards. Since the invention of the five-card trick, much effort has been devoted to devising efficient AND, XOR, and copy protocols. Currently, we have several card-based protocols efficient enough for lay-people to easily execute in everyday life. Theoretically, combining these elementary protocols, we can securely compute any functions (including multiple-valued functions). In this talk, I briefly introduce the history of card-based cryptography as well as several useful card-based protocols, which can be easily executed by you.

Accompanying Workshop

In conjunction with the symposium, the following workshops will be held.

» 32nd International Workshop on Post-Binary ULSI Systems (May 21, 2023)

» Reed-Muller 2023 Workshop (May 24, 2023)

The 53rd International Symposium will take place from May 22 to 24, 2023 in Matsue, Shimane, Japan. Interested researchers are invited to submit original research papers, surveys, or tutorial papers.




      KDDI Foundation

SECOM Science and
	  Technology Foundation    The KAJIMA

Technical Supporters:

» Photos were added to the top page on June 11, 2023.

» Final Program was uploaded on May 14, 2023.

» Registration has started.

» The site for registration was open on Feb. 27, 2023.
Registration will start on March 1.

» Style of holding the symposium was posted on the top page on Feb. 14, 2023.

» The Call for Book Proposals site was open on Oct. 27, 2022.

» This site was open on June 27, 2022.

» Paper Submission Deadline:
   November 1, 2022 (extended*)
   Abstract: December 8, 2022
   Manuscript: December 15, 2022
   *It will NOT be extended.

» Notification of Acceptance:
   February 1, 2023

» Camera-Ready Version:
   March 1, 2023

» Author Registration Deadline*:
   March 15, 2023
   *It is NOT going to be extended!

» Early Registration Deadline:
   April 20, 2023

» ULSI Workshop:
   May 21, 2023

» Symposium:
   May 22-24, 2023

» Reed-Muller 2023 Workshop:
   May 24, 2023

|Final Program|